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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:21:13 08/12/2015 
-- Design Name: 
-- Module Name:    hello - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hello is
PORT(din, clk_0, clk_x, clr: in STD_LOGIC;
	cnt_0, cnt_x: out STD_LOGIC_VECTOR(31 downto 0));
end hello;

--architecture Behavioral of hello is
--
--signal cnt_0_signal : STD_LOGIC_VECTOR(31 downto 0);
--signal cnt_x_signal : STD_LOGIC_VECTOR(31 downto 0);
--
--component counter
--port (clk, clr, en : in STD_LOGIC;
--	cnt : buffer STD_LOGIC_VECTOR (31 downto 0));
--end component;
--
--begin
--
--counter_0 : counter port map (clk=>clk_0, clr=>clr, en=>din, cnt=>cnt_0_signal);
----counter_x : counter port map (clk=>clk_x, clr=>clr, en=>din, cnt<=cnt_x_signal);
--
--cnt_0 <= cnt_0_signal;
--cnt_x <= cnt_x_signal;
--
--end Behavioral;
